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【压缩文件】 Vivado
收录时间:2020-01-31 文档个数:4 文档大小:11.4 GB 最近下载:2024-10-06 人气:5509 磁力链接
  • isoXilinx_Vivado_SDK_2015.4_1118_2.iso 11.4 GB
  • exeActivation/licgen_HLS.exe 295.9 kB
  • licActivation/ise_vivado_petalinux.lic 661 Bytes
  • txtActivation/Readme.txt 228 Bytes
【其他】 Xilinx Vivado Beginners Course to FPGA Development in VHDL
收录时间:2020-02-07 文档个数:3 文档大小:447.2 MB 最近下载:2024-10-07 人气:2264 磁力链接
  • tgzBeginners Course to FPGA Development in VHDL.tgz 447.2 MB
  • txtTorrent Downloaded From ExtraTorrent.cc.txt 352 Bytes
  • txtTorrent downloaded from demonoid.pw.txt 46 Bytes
【压缩文件】 Xilinx Vivado Design Suite 2014.2 ISO-TBE- [MUMBAI-TPB]
收录时间:2020-02-07 文档个数:3 文档大小:5.3 GB 最近下载:2024-10-06 人气:2892 磁力链接
  • isoXILINX_Vivado_DS_20142.iso 5.3 GB
  • nfotbe.nfo 12.1 kB
  • txtFollow Me.txt 314 Bytes
【影视】 [udemy] Xilinx Vivado Beginners Course to FPGA Development in VHDL [MyFOM]
收录时间:2020-02-28 文档个数:15 文档大小:483.8 MB 最近下载:2024-10-08 人气:5542 磁力链接
  • mp4Section 2 Lab 1/Implementation of VHDL Design in Vivado and IO Pin Planning.mp4 72.5 MB
  • mp4Section 4 Lab 3/Designing a Microblaze Soft Processor in Vivado IP Integrator.mp4 62.0 MB
  • mp4Section 4 Lab 3/Learn VHDL by Example.mp4 60.0 MB
  • mp4Section 3 Lab 2/Design a Block RAM in IP Integrator.mp4 53.0 MB
  • mp4Section 2 Lab 1/Downloading the Bit-stream to the FPGA.mp4 48.5 MB
  • mp4Section 2 Lab 1/Introduction to the Vivado Design Suite Interface and Creating a New Project.mp4 47.8 MB
  • mp4Section 1 Introduction to Vivado/How to Download and Install Xilinx Vivado Design Suite.mp4 42.2 MB
  • mp4Section 2 Lab 1/Coding and Simulating Simple VHDL in Vivado.mp4 36.2 MB
  • mp4Section 3 Lab 2/Simulating BRAM memory IP in Vivado.mp4 23.3 MB
  • mp4Section 4 Lab 3/Generating a Microblaze using TCL commands in Vivado.mp4 21.1 MB
  • mp4Section 1 Introduction to Vivado/Introduction.mp4 16.9 MB
  • htmlMyFreeOnlineMovies.co.uk.html 189.0 kB
  • txtTorrent Downloaded from Glodls.to.txt 237 Bytes
  • txtSection 4 Lab 3/New Text Document.txt 52 Bytes
  • txtSection 5 Conclusion and Bonus Section/Sorry the files are deleted bare with me.txt 51 Bytes
【影视】 vivado videos
收录时间:2020-04-11 文档个数:19 文档大小:895.9 MB 最近下载:2024-10-02 人气:1066 磁力链接
  • mp4[MP4 480p] Lecture -20 Discrete Wavelet Transforms.mp4 263.4 MB
  • mp4[MP4 1080p] Building a Hardware and Software Project _ Targeting the Zynq ZC702 Evaluation Kit.mp4 194.9 MB
  • mp4[MP4 1080p] Getting Started with Vivado High-Level Synthesis.mp4 90.6 MB
  • mp4[MP4 480p] How to Implement discrete wavelet transformation on image by matlab (Encode)【如何使用matlab來實作離散小波轉換】.mp4 75.2 MB
  • mp4[MP4 1080p] Working with System Generator for DSP and Platform Design Flows from IP Integrator.mp4 55.5 MB
  • mp4[MP4 Audio] Lecture -20 Discrete Wavelet Transforms.mp4 52.6 MB
  • mp4Xilinx HLS 2 FPGA FIR Filter Design in C in 30 minutes (Vivado High Level Synthesis).mp4 33.1 MB
  • mp4[MP4 1080p] A Look at MATLAB HDL Coder _ Turning MATLAB Into VHDL.mp4 21.9 MB
  • mp4[MP4 Audio] Building a Hardware and Software Project _ Targeting the Zynq ZC702 Evaluation Kit.mp4 20.1 MB
  • mp4[MP4 Audio] How to Implement discrete wavelet transformation on image by matlab (Encode)【如何使用matlab來實作離散小波轉換】.mp4 18.6 MB
  • mp4[MP4 1080p] VHDL#3 - How to simulate VHDL using Vivado.mp4 15.1 MB
  • mp4[MP4 1080p] Using Hardware Co Simulation with Vivado System Generator for DSP.mp4 13.5 MB
  • mp4[MP4 Audio] Working with System Generator for DSP and Platform Design Flows from IP Integrator.mp4 11.7 MB
  • mp4[MP4 Audio] Getting Started with Vivado High-Level Synthesis.mp4 10.3 MB
  • mp4[MP4 Audio] A Look at MATLAB HDL Coder _ Turning MATLAB Into VHDL.mp4 8.1 MB
  • mp4[MP4 Audio] Using Hardware Co Simulation with Vivado System Generator for DSP.mp4 5.6 MB
  • mp4[MP4 Audio] VHDL#3 - How to simulate VHDL using Vivado.mp4 2.0 MB
  • mp4[MP4 480p] Discrete Wavelet Transform DWT.mp4 2.0 MB
  • mp4[MP4 Audio] Discrete Wavelet Transform DWT.mp4 1.6 MB
【压缩文件】 [ FreeCourseWeb.com ] Udemy - Xilinx VIVADO Beginner Course for FPGA Development in VHDL.zip
收录时间:2020-06-28 文档个数:1 文档大小:309.8 MB 最近下载:2024-10-03 人气:2694 磁力链接
  • zip[ FreeCourseWeb.com ] Udemy - Xilinx VIVADO Beginner Course for FPGA Development in VHDL.zip 309.8 MB
【压缩文件】 [ DevCourseWeb.com ] Udemy - VIVADO - Learn From The Beginning! (With PCIe Full Project).zip
收录时间:2021-01-13 文档个数:1 文档大小:4.4 GB 最近下载:2024-09-29 人气:1800 磁力链接
  • zip[ DevCourseWeb.com ] Udemy - VIVADO - Learn From The Beginning! (With PCIe Full Project).zip 4.4 GB
【压缩文件】 [ FreeCourseWeb.com ] Udemy - Getting Started with Xilinx Zynq SoC Devices with Vivado.zip
收录时间:2021-02-18 文档个数:1 文档大小:3.8 GB 最近下载:2024-09-17 人气:2668 磁力链接
  • zip[ FreeCourseWeb.com ] Udemy - Getting Started with Xilinx Zynq SoC Devices with Vivado.zip 3.8 GB
【压缩文件】 [ DevCourseWeb.com ] Udemy - Xilinx Vivado Essentials for the Logic Designer.zip
收录时间:2021-03-06 文档个数:1 文档大小:1.2 GB 最近下载:2024-10-08 人气:10543 磁力链接
  • zip[ DevCourseWeb.com ] Udemy - Xilinx Vivado Essentials for the Logic Designer.zip 1.2 GB
【压缩文件】 Xilinx Vivado Design Suite 2014.2 ISO-TBE- [MUMBAI-TPB]
收录时间:2021-06-02 文档个数:5 文档大小:5.3 GB 最近下载:2024-01-14 人气:5 磁力链接
  • isoXILINX_Vivado_DS_20142.iso 5.3 GB
  • torrentXILINX_Vivado_DS_20142.iso.torrent 13.0 kB
  • nfotbe.nfo 12.1 kB
  • licXilinx.lic 1.4 kB
  • txtFollow Me.txt 314 Bytes
【压缩文件】 [ FreeCourseWeb.com ] Udemy - Designing a Processor with VHDL and Xilinx Vivado.rar
收录时间:2021-06-12 文档个数:1 文档大小:1.5 GB 最近下载:2024-10-09 人气:3655 磁力链接
  • rar[ FreeCourseWeb.com ] Udemy - Designing a Processor with VHDL and Xilinx Vivado.rar 1.5 GB
【其他】 vivado 2021.1
收录时间:2021-11-02 文档个数:1 文档大小:57.0 GB 最近下载:2024-10-08 人气:21997 磁力链接
  • 1vivado 2021.1 57.0 GB
【影视】 VHDL Circuit Design and FPGAs with VIVADO and MODELSIM
收录时间:2022-11-24 文档个数:171 文档大小:10.5 GB 最近下载:2024-09-21 人气:415 磁力链接
  • mp403 - Combinational Circuit Design in VHDL/003 VIVADO Application_ Generate Statement, MUX 2x1 and When-Else statement.mp4 517.6 MB
  • mp402 - Entity, Architecture and VHDL Operators/008 VIVADO Application_ Shift operators and abs() function simulation in VIVADO.mp4 515.7 MB
  • mp403 - Combinational Circuit Design in VHDL/006 VIVADO Application_ IO Planning Using Vivado.mp4 492.8 MB
  • mp407 - Sequential circuits, process, clock divider, sample seq. circ. implementations/006 VIVADO Application_ Parallel Operation, Signal Objects vs Variable Objects.mp4 450.9 MB
  • mp402 - Entity, Architecture and VHDL Operators/006 VIVADO Application_ Negative Numbers in VHDL, Positive and Natural Numbers.mp4 378.9 MB
  • mp402 - Entity, Architecture and VHDL Operators/011 VIVADO Application_ Power operator __, rem() and mod() simulation in VIVADO.mp4 365.3 MB
  • mp404 - Simulation of VHDL Programs, and Testbench Writing/003 VIVADO Application_ Writing TEST-BENCH and VIVADO Simulation Using TEST-BENCH.mp4 355.3 MB
  • mp413 - Fixed and Floating Point Numbers in VHDL/001 Simulation of Fixed-Point VHDL Implementations in VIVADO.mp4 354.5 MB
  • mp402 - Entity, Architecture and VHDL Operators/004 VIVADO Application_ Creating I_O Ports for Different Data Types and Port Pin Num.mp4 354.4 MB
  • mp411 - Intellectual Property (IP) Cores, and Use of IP Cores for VHDL Design/001 VIVADO Application_ Add_Subtract IP Code use in VHDL Code.mp4 333.7 MB
  • mp406 - User Defined Data Types, Constrained and Unconstrained Arrays, Matrices in VHDL/003 Matrices and 3D arrays in VHDL.mp4 276.4 MB
  • mp412 - Programming FPGA Using ARTY-7 35T Evaluation Board and VIvado/001 Constraints Files Used For the Programming of FPGAs.mp4 272.0 MB
  • mp407 - Sequential circuits, process, clock divider, sample seq. circ. implementations/011 MODELSIM Simulation_ Clock Division in VHDL, Part-1.mp4 261.0 MB
  • mp407 - Sequential circuits, process, clock divider, sample seq. circ. implementations/009 MODELSIM Simulation_ Signal Object Behavior-2.mp4 251.5 MB
  • mp410 - Packages, Components, Functions, Procedures/004 VIVADO Application_ Defining components and using them in VHDL codes.mp4 246.3 MB
  • mp412 - Programming FPGA Using ARTY-7 35T Evaluation Board and VIvado/002 Programming FPGA Using ARTY-7 35T Evaluation Board and XILINX VIVADO.mp4 240.4 MB
  • mp403 - Combinational Circuit Design in VHDL/008 Binary Encoders in VHDL.mp4 223.3 MB
  • mp406 - User Defined Data Types, Constrained and Unconstrained Arrays, Matrices in VHDL/004 MODELSIM Simulation for user-defined data type attributes.mp4 208.7 MB
  • mp409 - Loops in VHDL/001 Loops in VHDL.mp4 178.0 MB
  • mp404 - Simulation of VHDL Programs, and Testbench Writing/001 Testbench writing for the simulation of VHDL programs.mp4 175.3 MB
【影视】 [ DevCourseWeb.com ] Udemy - Learn Vivado from Top to Bottom - Your Complete Guide
收录时间:2022-12-08 文档个数:1 文档大小:983.5 MB 最近下载:2024-10-04 人气:1703 磁力链接
  • com ] Udemy - Learn Vivado from Top to Bottom - Your Complete Guide[ DevCourseWeb.com ] Udemy - Learn Vivado from Top to Bottom - Your Complete Guide 983.5 MB
【影视】 [ DevCourseWeb.com ] Udemy - Vivado 2020 - Learn Fpga Development Today!
收录时间:2023-02-18 文档个数:63 文档大小:669.5 MB 最近下载:2024-10-09 人气:4816 磁力链接
  • mp4~Get Your Files Here !/3 - VHDL/13 - Implement your design.mp4 55.5 MB
  • mp4~Get Your Files Here !/5 - Processor options/20 - Testing and Simulating.mp4 51.6 MB
  • mp4~Get Your Files Here !/3 - VHDL/12 - Simulating your VHDL code.mp4 48.6 MB
  • mp4~Get Your Files Here !/5 - Processor options/26 - Generate HDL commands from c based code.mp4 39.2 MB
  • mp4~Get Your Files Here !/5 - Processor options/24 - Implement a Micro blaze soft Processor.mp4 38.5 MB
  • mp4~Get Your Files Here !/4 - Memory/19 - Creating a memory block in the integrator.mp4 36.2 MB
  • mp4~Get Your Files Here !/3 - VHDL/10 - Creating your first project in Vivado.mp4 33.2 MB
  • mp4~Get Your Files Here !/3 - VHDL/8 - Intro to VHDL.mp4 30.4 MB
  • mp4~Get Your Files Here !/1 - Introduction/1 - The digital design fundamentals you must learn.mp4 25.8 MB
  • mp4~Get Your Files Here !/2 - Digital systems/2 - Analog and Digital Systems.mp4 24.2 MB
  • mp4~Get Your Files Here !/4 - Memory/17 - IP integrator in Vivado.mp4 24.0 MB
  • mp4~Get Your Files Here !/5 - Processor options/25 - Learn TCL Commands to generate Micro blaze soft processor.mp4 23.8 MB
  • mp4~Get Your Files Here !/2 - Digital systems/5 - Download and install Vivado.mp4 20.6 MB
  • mp4~Get Your Files Here !/4 - Memory/16 - IP Flows.mp4 19.6 MB
  • mp4~Get Your Files Here !/5 - Processor options/23 - Processor Options.mp4 18.3 MB
  • mp4~Get Your Files Here !/4 - Memory/18 - Memory Controllers.mp4 18.1 MB
  • mp4~Get Your Files Here !/6 - Conclusion/29 - Conclusion.mp4 18.0 MB
  • mp4~Get Your Files Here !/3 - VHDL/9 - FPGA Design Flow.mp4 17.2 MB
  • mp4~Get Your Files Here !/2 - Digital systems/4 - FPGA Architecture.mp4 17.0 MB
  • mp4~Get Your Files Here !/3 - VHDL/11 - Vivado Design Tools.mp4 16.8 MB
【影视】 [ DevCourseWeb.com ] Udemy - PYNQ FPGA Development with Python Programming and VIVADO
收录时间:2023-08-20 文档个数:145 文档大小:2.0 GB 最近下载:2024-10-09 人气:4574 磁力链接
  • mp4~Get Your Files Here !/6. Section 6 Creating Custom Overlay (VIVADO Project) for PYNQ/1. Creating Custom Overlay on PYNQ Addition & Multiplication Application.mp4 197.3 MB
  • mp4~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/3. Section3_2 Python OpenCV Development with PYNQ FPGA Part I OpenCV Basics.mp4 152.3 MB
  • mp4~Get Your Files Here !/5. Section 5 Machine Learning with Python in PYNQ/1. Machine Learning with Python.mp4 146.8 MB
  • mp4~Get Your Files Here !/7. Section 7 Creating Custom Python Function Accelerator on PYNQ with VIVADO tool/1. Accelerating Custom Image Processing Function on PYNQ.mp4 145.5 MB
  • mp4~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/1. Section3_0_Python_Overview.mp4 143.1 MB
  • mp4~Get Your Files Here !/1. Introduction to PYNQ Architecture/1. PYNQ FPGA Introduction Part I.mp4 130.3 MB
  • mp4~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/5. Python OpenCV HDMI Streaming & Processing.mp4 129.8 MB
  • mp4~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/2. Section3_1 Python Programming, Conditional Statements and Loops with PYNQ GPIO.mp4 124.8 MB
  • mp4~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/4. Section3_2 Python OpenCV Development with PYNQ Part II Face & Eye Detection.mp4 117.7 MB
  • mp4~Get Your Files Here !/1. Introduction to PYNQ Architecture/3. Section 1 PYNQ Boards & Accessories [Demo].mp4 114.8 MB
  • mp4~Get Your Files Here !/1. Introduction to PYNQ Architecture/2. PYNQ Introduction Part II.mp4 102.0 MB
  • mp4~Get Your Files Here !/2. PYNQ Development Methodologies/2. PYNQ FPGA Board Setup & Basic Programming Demo.mp4 101.2 MB
  • mp4~Get Your Files Here !/2. PYNQ Development Methodologies/1. PYNQ Development Methodologies Overview.mp4 98.9 MB
  • mp4~Get Your Files Here !/1. Introduction to PYNQ Architecture/4. PYNQ-Z2 Unboxing and Demo [Optional].mp4 97.4 MB
  • mp4~Get Your Files Here !/6. Section 6 Creating Custom Overlay (VIVADO Project) for PYNQ/3. Creating PYNQ VDMA Overlay with VIVADO 2021.1 and Python-Notebook.mp4 89.4 MB
  • mp4~Get Your Files Here !/4. Section 4 Installing Python Library in PYNQ/1. Installing Cryptography Python Library on PYNQ.mp4 55.9 MB
  • mp4~Get Your Files Here !/3. Section 3 PYNQ with Python_OpenCV for Image Processing & Video_processing/6. PYNQ-License Plate Localizer on Python OpenCV.mp4 42.9 MB
  • bit~Get Your Files Here !/6. Section 6 Creating Custom Overlay (VIVADO Project) for PYNQ/PYNQ_VDMA_Overlay_Sources_HWH_BIT_IPYNB_JPG_S9_2021/vdma/vdma.bit 4.0 MB
  • bit~Get Your Files Here !/7. Section 7 Creating Custom Python Function Accelerator on PYNQ with VIVADO tool/project_resizer/resizer.bit 4.0 MB
  • ipynb~Get Your Files Here !/5. Section 5 Machine Learning with Python in PYNQ/Char_Recognition_with_PYNQ_V2.ipynb 3.7 MB
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