2048BT

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【压缩文件】 [ FreeCourseWeb.com ] Udemy - Learn VHDL Design using Xilinx Zynq-7000 ARM-FPGA SoC.zip
收录时间:2020-04-14 文档个数:1 文档大小:1.6 GB 最近下载:2024-09-28 人气:6463 磁力链接
  • zip[ FreeCourseWeb.com ] Udemy - Learn VHDL Design using Xilinx Zynq-7000 ARM-FPGA SoC.zip 1.6 GB
【压缩文件】 [ DevCourseWeb.com ] Udemy - Getting Started with Custom AXI peripherals for Zynq Devices.zip
收录时间:2021-02-04 文档个数:1 文档大小:1.8 GB 最近下载:2024-06-02 人气:165 磁力链接
  • zip[ DevCourseWeb.com ] Udemy - Getting Started with Custom AXI peripherals for Zynq Devices.zip 1.8 GB
【压缩文件】 [ FreeCourseWeb.com ] Udemy - Getting Started with Xilinx Zynq SoC Devices with Vivado.zip
收录时间:2021-02-18 文档个数:1 文档大小:3.8 GB 最近下载:2024-09-17 人气:2668 磁力链接
  • zip[ FreeCourseWeb.com ] Udemy - Getting Started with Xilinx Zynq SoC Devices with Vivado.zip 3.8 GB
【影视】 Embedded System Design with Zynq Devices for Newbie
收录时间:2021-06-05 文档个数:142 文档大小:3.3 GB 最近下载:2024-09-28 人气:3209 磁力链接
  • mp4[TutsNode.com] - Embedded System Design with Zynq Devices for Newbie/8. Getting started with Interrupts/3. Using GPIO Interrupt P2.mp4 229.0 MB
  • mp4[TutsNode.com] - Embedded System Design with Zynq Devices for Newbie/2. Getting Started with Simple Peripherals GPIO/4. Working with GPIO LED's.mp4 220.3 MB
  • mp4[TutsNode.com] - Embedded System Design with Zynq Devices for Newbie/8. Getting started with Interrupts/6. Handling Multiple Interrupts.mp4 205.0 MB
  • mp4[TutsNode.com] - Embedded System Design with Zynq Devices for Newbie/5. Software and Hardware Debugging/6. Getting Started with Integrated Logic Analyzer (ILA).mp4 165.3 MB
  • mp4[TutsNode.com] - Embedded System Design with Zynq Devices for Newbie/4. Getting started with Intermediate Drivers Understanding Timers/1. Using Watchdog Timer in Watchdog mode.mp4 152.8 MB
  • mp4[TutsNode.com] - Embedded System Design with Zynq Devices for Newbie/9. Fundamentals of Timers AXI Timer, SCU Timer and Watchdog/11. Using Triple Timer Counter in Interval mode with Interrupts.mp4 150.8 MB
  • mp4[TutsNode.com] - Embedded System Design with Zynq Devices for Newbie/2. Getting Started with Simple Peripherals GPIO/6. Understanding handling multiple instances of IP's.mp4 139.1 MB
  • mp4[TutsNode.com] - Embedded System Design with Zynq Devices for Newbie/4. Getting started with Intermediate Drivers Understanding Timers/3. SCU Timer in Polled Mode.mp4 137.2 MB
  • mp4[TutsNode.com] - Embedded System Design with Zynq Devices for Newbie/9. Fundamentals of Timers AXI Timer, SCU Timer and Watchdog/9. Reusing SCU Timer Interrupt Code for Watchdog Timer.mp4 122.9 MB
  • mp4[TutsNode.com] - Embedded System Design with Zynq Devices for Newbie/9. Fundamentals of Timers AXI Timer, SCU Timer and Watchdog/7. Using SCU Timer in Interrupt Mode.mp4 122.6 MB
  • mp4[TutsNode.com] - Embedded System Design with Zynq Devices for Newbie/7. Understanding Memory Resources/2. Using AXI BRAM with pointers P2.mp4 114.9 MB
  • mp4[TutsNode.com] - Embedded System Design with Zynq Devices for Newbie/3. Getting started with Intermediate Drivers UARTPS/2. Writing Data with UARTPS Drivers.mp4 113.9 MB
  • mp4[TutsNode.com] - Embedded System Design with Zynq Devices for Newbie/9. Fundamentals of Timers AXI Timer, SCU Timer and Watchdog/2. Using AXI Timer IP P2 Understanding Down Mode.mp4 103.5 MB
  • mp4[TutsNode.com] - Embedded System Design with Zynq Devices for Newbie/7. Understanding Memory Resources/5. Handling DDR Transactions.mp4 89.4 MB
  • mp4[TutsNode.com] - Embedded System Design with Zynq Devices for Newbie/6. Profiling/1. Understanding Profiling feature of SDK.mp4 83.1 MB
  • mp4[TutsNode.com] - Embedded System Design with Zynq Devices for Newbie/7. Understanding Memory Resources/7. Handling DDR to BRAM Transactions.mp4 79.8 MB
  • mp4[TutsNode.com] - Embedded System Design with Zynq Devices for Newbie/2. Getting Started with Simple Peripherals GPIO/7. Using Multichannel GPIO Instance.mp4 78.6 MB
  • mp4[TutsNode.com] - Embedded System Design with Zynq Devices for Newbie/1. Toolchain Configuration/1. Introduction.mp4 76.8 MB
  • mp4[TutsNode.com] - Embedded System Design with Zynq Devices for Newbie/7. Understanding Memory Resources/3. Understanding XIL_IO Drivers.mp4 75.5 MB
  • mp4[TutsNode.com] - Embedded System Design with Zynq Devices for Newbie/5. Software and Hardware Debugging/5. Using XSCT Console.mp4 74.5 MB
【影视】 [ DevCourseWeb.com ] Udemy - Building Custom AXI Interface Peripherals for ZYNQ Devices
收录时间:2022-05-04 文档个数:131 文档大小:3.2 GB 最近下载:2024-09-28 人气:3551 磁力链接
  • mp4~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/37 - Using Vivado Interrupt Template Code P2.mp4 224.0 MB
  • mp4~Get Your Files Here !/8 - Adding Master Interface/45 - Creating Master Interface with Vivado Template P1.mp4 170.4 MB
  • mp4~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/42 - Blinking Effect with Interrupt.mp4 158.1 MB
  • mp4~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/33 - Adding Interrupt with RTL P2.mp4 156.5 MB
  • mp4~Get Your Files Here !/10 - AXI Stream Master Interface with Vivado Template/55 - Creating AXIS Master Interface P1.mp4 152.3 MB
  • mp4~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/49 - Building AXIS Slave Interface P1.mp4 145.6 MB
  • mp4~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/36 - Using Vivado Interrupt Template Code P1.mp4 104.9 MB
  • mp4~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/23 - Analyzing Signals on ILA Probe.mp4 102.9 MB
  • mp4~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/25 - Add Existing RTL Delay Generator P1.mp4 98.3 MB
  • mp4~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/32 - Adding Interrupt with RTL P1.mp4 94.8 MB
  • mp4~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/21 - Other Signals in Slave Lite Interface.mp4 93.9 MB
  • mp4~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/27 - Adding Existing RTL Multiplier P1.mp4 87.1 MB
  • mp4~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/31 - Fundamentals of Interrupt C Application.mp4 84.5 MB
  • mp4~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/7 - Slave Lite Interface without I O Ports P4 Creating C Application.mp4 80.0 MB
  • mp4~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/50 - Building AXIS Slave Interface P2.mp4 68.7 MB
  • mp4~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/52 - Building Complex FSM with existing FSM for AXIS.mp4 67.1 MB
  • mp4~Get Your Files Here !/8 - Adding Master Interface/46 - Creating Master Interface with Vivado Template P2.mp4 65.7 MB
  • mp4~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/60 - Building AXIS Slave Interface with Verilog P2.mp4 64.6 MB
  • mp4~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/64 - Building AXIS Master Slave Interface with Verilog P1.mp4 60.3 MB
  • mp4~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/39 - Modifying Delay of the Vivado Interrupt Template.mp4 58.0 MB

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